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Program Duration Batch Starts Time Price # Enroll Book free demo
Weekend
32 Hrs Weekend Evening-Batch INR 10000

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About Course

Engineers who seek advanced FPGA design training using Xilinx tools to improve FPGA performance and utilization while also increasing productivity
Essentials of FPGA Design
Designing for Performance
Intermediate knowledge of VHDL or Verilog is strongly recommended
At least six months of design experience with Xilinx tools and FPGAs

CURRICULUM

FPGA / VHDL / Verilog

  • 1.1 Introduction
  • 1.2 Lab 1: Timing Closure Review
  • 1.3 UCF Editing
  • 1.4 Lab 2: UCF Editing
  • 1.5 Advanced I/O Timing
  • 1.6 Lab 3: Advanced I/O Timing
  • 1.7 Tcl Scripting
  • 1.8 Lab 4: Tcl Scripting
  • 1.9 Floorplanning an Effective Layout
  • 1.10 Lab 5: Floorplanning
  • 1.11 Design Preservation Techniques
  • 1.12 FPGA Editor: Viewing and Editing a Routed Design
  • 1.13 Lab 6: Advanced FPGA Editor
  • Lab Descriptions
  • 1.14 Lab 1: Timing Closure Review – Use the Constraints Editor to enter timing constraints.
  • 1.15 Lab 2: UCF Editing – Write constraints directly into a UCF file to guide the performance results of implementation.
  • 1.16 Lab 3: Advanced I/O Timing – Compose timing constraints for source-synchronous and system-synchronous I/O interfaces. Analyze the timing and determine changes to optimize the interface timing.
  • 1.17 Lab 4: Tcl Scripting – Write ISE tool control commands in Tcl script files to create a project and implement the design. Explore how the Tcl interface is integrated with the Project Navigator tool.
  • 1.18 Lab 5: Floorplanning – Implement a design by using floorplanned constraints to improve the timing results over a design without floorplanning.
  • 1.19 Lab 6: FPGA Editor – Use the FPGA Editor to view and edit a design. Rapidly locate and swap signals of interest for ChipScope Pro tool cores.

Module

  • Day 1
  • 2.1 Hardware Modeling Overview
  • 2.2 Verilog Language Concepts
  • 2.3 Modules and Ports
  • 2.4 Demo: Multiplexer
  • 2.5 Lab 1: Building Hierarchy
  • 2.6 Introduction to Testbenches
  • 2.7 Lab 2: Verilog Simulation and RTL Verification
  • Day 2
  • 2.8 Verilog Operators and Expressions
  • 2.9 Continuous Assign Statements
  • 2.10 Lab 3: Creating a Simple Memory
  • 2.11 Verilog Procedural Statements
  • 2.12 Lab 4: Building the Clock Divider and Address Counter
  • 2.13 Controlled Operation Statements
  • 2.14 Lab 5: Creating an n-bit Binary Counter
  • Day 3
  • 2.15 Verilog Tasks and Functions
  • 2.16 Advanced Language Concepts
  • 2.17 Finite State Machines
  • 2.18 Lab 6 Building a Finite State Machine
  • 2.19 Targeting Xilinx FPGAs
  • 2.20 Lab 7: Implementing and Downloading the Design
  • 2.21 Advanced Verilog Testbenches
  • 2.22 Lab 8: Using Verilog File I/O
  • Lab Descriptions
  • 2.23 The labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. The labs are written, synthesized, behaviorally simulated, and implemented by the student. The focus of the labs is to write code that will optimally infer reliable and high-performance circuits. The labs culminate in a functional calculator that students verify in simulation.

Exam & Certification




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