Course Batch Starts, Timing, Price & Enroll

Program Duration Batch Starts Time Price # Enroll Book free demo
Weekend
32 Hrs Weekend Evening-Batch INR 10000

Enroll Now Book free demo class

# Cloud lab charges will be extra. Our technical consultant will share actual lab charges with you.

About Course

Engineers who seek advanced FPGA design training using Xilinx tools to improve FPGA performance and utilization while also increasing productivity
Essentials of FPGA Design
Designing for Performance
Intermediate knowledge of VHDL or Verilog is strongly recommended
At least six months of design experience with Xilinx tools and FPGAs

CURRICULUM

FPGA / VHDL / Verilog

  • 1.1 Introduction
  • 1.2 Lab 1: Timing Closure Review
  • 1.3 UCF Editing
  • 1.4 Lab 2: UCF Editing
  • 1.5 Advanced I/O Timing
  • 1.6 Lab 3: Advanced I/O Timing
  • 1.7 Tcl Scripting
  • 1.8 Lab 4: Tcl Scripting
  • 1.9 Floorplanning an Effective Layout
  • 1.10 Lab 5: Floorplanning
  • 1.11 Design Preservation Techniques
  • 1.12 FPGA Editor: Viewing and Editing a Routed Design
  • 1.13 Lab 6: Advanced FPGA Editor
  • Lab Descriptions
  • 1.14 Lab 1: Timing Closure Review – Use the Constraints Editor to enter timing constraints.
  • 1.15 Lab 2: UCF Editing – Write constraints directly into a UCF file to guide the performance results of implementation.
  • 1.16 Lab 3: Advanced I/O Timing – Compose timing constraints for source-synchronous and system-synchronous I/O interfaces. Analyze the timing and determine changes to optimize the interface timing.
  • 1.17 Lab 4: Tcl Scripting – Write ISE tool control commands in Tcl script files to create a project and implement the design. Explore how the Tcl interface is integrated with the Project Navigator tool.
  • 1.18 Lab 5: Floorplanning – Implement a design by using floorplanned constraints to improve the timing results over a design without floorplanning.
  • 1.19 Lab 6: FPGA Editor – Use the FPGA Editor to view and edit a design. Rapidly locate and swap signals of interest for ChipScope Pro tool cores.

Module

  • Day 1
  • 2.1 Hardware Modeling Overview
  • 2.2 Verilog Language Concepts
  • 2.3 Modules and Ports
  • 2.4 Demo: Multiplexer
  • 2.5 Lab 1: Building Hierarchy
  • 2.6 Introduction to Testbenches
  • 2.7 Lab 2: Verilog Simulation and RTL Verification
  • Day 2
  • 2.8 Verilog Operators and Expressions
  • 2.9 Continuous Assign Statements
  • 2.10 Lab 3: Creating a Simple Memory
  • 2.11 Verilog Procedural Statements
  • 2.12 Lab 4: Building the Clock Divider and Address Counter
  • 2.13 Controlled Operation Statements
  • 2.14 Lab 5: Creating an n-bit Binary Counter
  • Day 3
  • 2.15 Verilog Tasks and Functions
  • 2.16 Advanced Language Concepts
  • 2.17 Finite State Machines
  • 2.18 Lab 6 Building a Finite State Machine
  • 2.19 Targeting Xilinx FPGAs
  • 2.20 Lab 7: Implementing and Downloading the Design
  • 2.21 Advanced Verilog Testbenches
  • 2.22 Lab 8: Using Verilog File I/O
  • Lab Descriptions
  • 2.23 The labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. The labs are written, synthesized, behaviorally simulated, and implemented by the student. The focus of the labs is to write code that will optimally infer reliable and high-performance circuits. The labs culminate in a functional calculator that students verify in simulation.

Exam & Certification




SELECT TRAINER FOR DEMO


Vaibhav Mishra
Certification:
From
Professional Experience
Training Experience

Qualification
B.Tech and APGD in VLSI

Skills
Embedded, FPGA, VHDI, Verilog,

Profile
RATING & REVIEWS
Vaibhav Mishra
Certification:
From
Professional Experience
Training Experience

Qualification
B Tech and APGD in VLSI

Skills
Embedded, FPGA, Verilog, VHDI, VLSI,

Profile
10 years exp on FPGA . Running Own Academy , where is used to give training and placement . Looking for portal, where I can upload my skills and meet the audience requirement . Read More...
RATING & REVIEWS
Manish
Joining a course with Vaibhav give me a great platform to learn industry oriented and core electronics that help me to improve my academic and personal skills. he support me every time whenever i required. I would like to thanks Vaibhava sir to choose my carrier and get a job in core electronics field.
Mukesh
He helped me to choose my career in my core domain. Here I got the knowledge about semiconductor & FPGA industry. I suggest every electronics student to choose their career in electronics and join this course. I am thankful to Vaibhav Mishra sir for their hard effort from the start of the course.
Vivek Joshi
Being an unskilled son of B. TECH, it was a backbreaking task for me to get into core electronics industry so from 2nd to 3rd year i was preparing for gate, as time passes by it becomes apparent to me that clearing gate is one thing, securing good rank is another and then clearing an interview is something which is very close to impossible. At the beginning of 4th year i got to know about this new coaching institute which has an excellent faculty Vaibhawa Sir and Vaibhav Sir, I get enrolled myself and not only I learned a lot but also I enjoyed a lot, as time passes by the day has come when we have to go for interview, in this crucial juncture of time not only our friend like teachers are with us but they whole heartedly supported us, I want to say this to every student of CS and EC branch that getting a B. TECH degree is one thing and completing B. tech while also getting skills which makes you stand out from the crowd of thousands of engineers is another, so do something which is really fruitful for your future.
Sufiyan Safi
I got the rich domain knowledge with comprehensive understanding of ASIC layouts, Analog Design, Digital concepts during my training and the Scripting taught by Trainer is inimitable. These all helped me to go through all the technical rounds very smoothly and credit goes to our supportive trainers to share their valuable knowledge with us
Sweta singh
I always had a dream to make a place in core industry and hence I needed the skills, Mr. Vaibhav Mishra provided me the motivation. Here I get trained in a great deal of things from digital concepts to ASIC layouts and Analog design, and my favorite part, Scripting taught by a trainer in incredibly unique style. All in all, I am very thankful to my mentors, Vaibhav Mishra.
Sudhanshu Bhardwaj
The knowledge about the domain which I gained here, helped me in getting a job in the company of my dreams and all credit goes to Vaibhava Mishra Sir for delivering such a fantastic training.
Disclaimer

**

* Money Back Guarantee till demo and 1st class of the course.


Copyright ©2015 Hub4Tech.com, All Rights Reserved. Hub4Tech™ is registered trademark of Hub4tech Portal Services Pvt. Ltd.
All trademarks and logos appearing on this website are the property of their respective owners.
FOLLOW US