Course Batch Starts, Timing, Price & Enroll

Program Duration Batch Starts Time Price Enroll Book free demo
Weekend
40 Hrs Weekend Morning-Batch USD 400
INR 20000
Enroll Now Book free demo class

About Course

Engineers who are interested in developing embedded systems with the Xilinx Zynq All Programmable SoC or MicroBlaze soft processor core using the Embedded Development Kit.
FPGA design experience
Completion of the Essentials of FPGA Design course or equivalent knowledge of Xilinx ISE® software implementation tools
Basic understanding of C programming
Basic understanding of microprocessors
Some HDL modeling experience

CURRICULUM

Embedded

Module

  • 1.1 Embedded UltraFast Design Methodology
  • 1.2 Overview of Embedded Hardware Development
  • 1.3 Driving the IP Integrator Tool (Lab)
  • 1.4 Overview of Embedded Software Development
  • 1.5 Driving the SDK Tool (Lab)
  • 1.6 AXI: Introduction
  • 1.7 AXI: Variations
  • 1.8 AXI: Transactions (Lab)
  • 1.9 Introduction to Interrupts
  • 1.10 Interrupts: Hardware Architecture and Support

Module

  • 2.1 AXI: Connecting AXI IP
  • 2.2 Using the Create and Import Wizard to Create a New AXI IP (Lab)
  • 2.3 AXI: BFM Simulation (Lab)
  • 2.4 MicroBlaze Processor Architecture Overview (Lab)
  • 2.5 MicroBlaze Processor Block Memory Usage
  • 2.6 Zynq-7000 All Programmable SoC Architecture Overview (Lab)
  • 3.1 Driving the IP Integrator Tool: Introduction to the most commonly performed operations and capabilities of the Vivado IP integrator tool.
  • 3.2 Driving the SDK Tool: Introduction to the basic operations of SDK. Concepts such as project creation, adding existing source code to an application, compilation and linking, and downloading are covered.
  • 3.3 Exploring AXI Transactions Using the AXI Traffic Generator: AXI4 transactions will be explored in this lab with special emphasis on AXI channels, handshaking, and the most useful signal members within the AXI interface.
  • 3.4 The AXI Traffic Generator (ATG) IP example design will serve as the basis of this lab. Simulation of the design will provide the sample AXI traffic to be studied.
  • 3.5 Building Custom AXI IP: This lab guides you through the process of creating and adding a custom AXI peripheral to the Vivado IP catalog by using the Create and Package IP Wizard. The focus is on the process of adding an AXI interface onto an existing peripheral—not the actual design of the peripheral logic.
  • 3.6 BFM Simulation: BFM simulations are used to generate bus stimulus and observe the response to that stimulus. Here you will learn how to run a BFM simulation for a custom peripheral.
  • 3.7 Exploring the Architecture of the MicroBlaze Processor: Some of the configurable options in the MicroBlaze processor are introduced in this lab. You will learn how to instantiate and configure the MicroBlaze processor and use Designer Assistance to complete a design.
  • 3.8 Exploring the Architecture of the Zynq-7000 All Programmable SoC: This introduction to the basic process of instantiating and customizing the processor system (PS) of the Zynq-7000 All Programmable SoC family of parts illustrates the process of customizing the PS. While not every aspect of customization is covered, the processes provided here can be extended to all aspects of customization.

Exam & Certification


POWER OF CHOOSING YOUR TRAINER - TAKE DEMO FROM 3 TRAINERS AND SELECT


Disclaimer

**

* Money Back Guarantee till demo and 1st class of the course.


Copyright ©2015 Hub4Tech.com, All Rights Reserved. Hub4Tech™ is registered trademark of Hub4tech Portal Services Pvt. Ltd.
All trademarks and logos appearing on this website are the property of their respective owners.
FOLLOW US